The present invention relates generally to array circuit designs, and more specifically to reduce power consumption during computer data storage.
Static Random Access Memory (SRAM) is a type of computer data storage which does not require frequent refreshing. Furthermore, the data/information from one zone within the computer memory does not need to be read and rewritten to the same zone every so often, and thus described in the art as “static.” SRAM is used for a CPU cache. SRAM is volatile in the conventional sense in that data is eventually lost when the memory is not powered while exhibiting data remanence, (i.e., the residual representation of digital data that remains after attempts have been made to remove or erase the data). By applying bi-stable latching circuitry, SRAM stores bits (i.e., a basic unit of information in computing) as data storage elements. A latch or a flip-flop of the SRAM (which is a circuit by design) stores state information on each bit. The binary nature of these bits is represented in terms of two states—“zero” or “one.” In other words, each bit is in the “zero” state or the “one” state.